1. Field of the Invention
The present invention relates to a shift register of a liquid crystal display (LCD) device, and more particularly, to a shift register which can prevent a multi-output caused by a coupling phenomenon.
2. Discussion of the Related Art
In general, a liquid crystal display (LCD) device displays images by controlling light transmittance of liquid crystal with the use of an electric field. For this, the LCD device is provided with an LCD panel including a plurality of pixel regions arranged in a matrix, and a driving circuit for driving the LCD panel.
The LCD panel comprises a plurality of gate lines crossing a plurality of data lines to define a plurality of pixel regions. A thin film transistor (TFT) is provided in each pixel region. A plurality of pixel electrodes and a common electrode are formed in the LCD panel to apply the electric field to the respective pixel regions. Each of the pixel electrodes is connected with one of the data lines through drain and source terminals of the corresponding thin film transistor (TFT) which functions as a switching device. The thin film transistor (TFT) is turned-on by an output pulse applied to a gate terminal thereof through the gate line, while a data signal from the data line is charged in a pixel voltage.
The driving circuit comprises a gate driver for driving the gate lines; a data driver for driving the data lines; a timing controller for supplying control signals to control the gate and data drivers; and a power supply for supplying driving voltages for the LCD device.
The timing controller controls the driving timing of the gate and data drivers, and supplies pixel data signals to the data driver. The power supply generates driving voltages such as a common voltage, a gate high-voltage signal (VGH) and a gate low-voltage signal (VGL) by raising or reducing an input power. The gate driver supplies output pulses to the gate lines in sequence, to thereby sequentially drive liquid crystal cells of the LCD panel by one line. The data driver supplies a pixel voltage signal to each of the data lines whenever the output pulse is supplied to any one of the gate lines. Accordingly, the LCD device displays images by controlling the light transmittance with the electric field applied between the pixel electrode and the common electrode according to the pixel voltage signal by each liquid crystal cell.
At this time, the gate driver comprises a shift register to output the scan pulses in sequence. The related art shift register is comprised of ‘n’ stages which are subordinately connected to one another. In this case, each of the stages outputs one scan pulse. The scan pulses outputted from the respective stages are sequentially supplied to the gate lines of the LCD panel (not shown), to thereby scan the gate lines in sequence.
FIG. 1 illustrates a circuit structure included in a stage according to the related art. Each stage is comprised of a node control unit 101 which controls the charge and discharge state in an enable node (Q) and a disable node (QB); a pull-up switching unit (Trpu) which outputs an output pulse (Vout) according to the signal state of the enable node (Q); and a pull-down switching unit (Trpd) which outputs a discharging voltage source (VSS) according to the signal state of the disable node (QB). At this time, the enable node (Q) and the disable node (QB) are alternately charged and discharged. In detail, when the enable node (Q) is charged, the disable node (QB) is discharged. In the meantime, when the disable node (QB) is charged, the enable node (Q) is discharged. Also, when the enable node (Q) is charged, the pull-up switching unit (Trpu) outputs the output pulse (Vout). When the disable node (QB) is charged, the pull-down switching unit (Trpd) outputs the discharging voltage source (VSS).
Then, the output pulse (Vout) outputted from the pull-up switching unit (Trpu) and the discharging voltage source (VSS) outputted from the pull-down switching unit (Trpd) are supplied to the corresponding gate line. At this time, a gate terminal of the pull-up switching unit (Trpu) is connected with the enable node (Q); a drain terminal of the pull-up switching unit (Trpu) is connected with a clock transmission line to which the clock pulse is applied; and a source terminal of the pull-up switching unit (Trpu) is connected with the gate line. The clock pulse (CLK) is provided with the high and low states periodically, and the clock pulse (CLK) is supplied to the drain terminal of the pull-up switching unit (Trpu). At this time, the pull-up switching unit (Trpu) outputs any one of the high-state clock pulses (CLK) inputted by each period at a predetermined point. The clock pulse (CLK) outputted at the predetermined point corresponds to the output pulse (Vout) to drive the gate line.
The predetermined point corresponds to a point in which the enable node (Q) is charged. That is, among the clock pulses (CLK) periodically inputted to the drain terminal of the pull-up switching unit (Trpu), the pull-up switching unit (Trpu) outputs the high-state clock pulse (CLK) inputted at the predetermined point (the point in which the enable node (Q) is charged) as the output pulse (Vout). According as the enable node (Q) is maintained as the discharge state until the next frame is started after the output of the output pulse (Vout), the pull-up switching unit (Trpu) outputs one output pulse (Vout) by each frame. However, since the clock pulse (CLK) is outputted several times during one frame, the clock pulse (CLK) is continuously inputted to the drain terminal of the pull-up switching unit (Trpu) even in the turn-off state of the pull-up switching unit (Trpu), i.e., even in the discharge state of the enable node (Q). In other words, the pull-up switching unit (Trpu) is turned-on once during one frame, and also the pull-up switching unit outputs the clock pulse (CLK), which is inputted to its own drain terminal during the turn-on period, as the output pulse (Vout).
After that, the pull-up switching unit (Trpu) is turned-off until the next frame is started. Thus, the pull-up switching unit can not output the clock pulse (CLK) as the output pulse (Vout) even though the clock pulse is inputted to the drain terminal of the pull-up switching unit during the turn-off period. According as the clock pulse (CLK) is periodically applied to the drain terminal of the pull-up switching unit (Trpu), the coupling phenomenon occurs between the enable node (Q) connected with the gate terminal of the pull-up switching unit (Trpu) and the drain terminal of the pull-up switching unit (Trpu). By the coupling phenomenon, the enable node (Q) is continuously charged with the predetermined voltage according to the clock pulse (CLK). That is, the enable node (Q) is maintained in the charge state even at the undesired timing. In this case, the enable node (Q) may be charged two or more times during one frame, whereby the pull-up switching unit (Trpu) may be turned-on two or more times during one frame. Eventually, one stage outputs the output pulses (Vout) two or more times during one frame, thereby causing the multi-output. Accordingly, if one stage outputs the output pulses (Vout) two or more times during one frame, the picture quality of images displayed on the LCD panel is deteriorated.